This invention relates to logic design systems for programmable logic devices, and more particularly to systems and methods for configuring programmable logic to minimize leakage current.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired logic design. In a typical scenario, a logic designer uses a logic design system to design a logic circuit. The logic design system uses information on the hardware capabilities of a given programmable logic device to help the designer implement the logic circuit using the resources available on that given programmable logic device.
As semiconductor fabrication methods improve, it is becoming possible to fabricate transistors and other integrated circuit components with increasingly small dimensions. It is generally desirable to shrink component sizes as much as possible to reduce costs and improve performance. However, as transistor gates become smaller, they become less effective at turning transistors off. This can lead to undesirable gate leakage effects that increase the power consumption of an integrated circuit.
Hardware-based approaches can help reduce gate leakage. However, hardware-based approaches can result in an increase in circuit overhead and complexity.
It would therefore be desirable to provide improved ways in which to reduce power consumption due to gate leakage effects in programmable logic devices.